//Stephen Kirksharian
//Robert Harkreader
//CPSC 321
//DUE 4/27/08

// Texas A&M University          //
// cpsc321 Computer Architecture //
// $Id: mux.v,v 1.1 2001/11/07 19:24:39 miket Exp miket $ //
// Multiplexers of various bit-sizes and input to output mapping //
module MUX1_3to1(AA0,AA1,AA2,select,out);
	input AA0,AA1,AA2;
	input [1:0]select;
	output out;
	reg out;

always @(AA0 or AA1 or AA2 or select) begin
	if(select==0) out=AA0;
	else if(select==1) out=AA1;
	else if(select==2) out=AA2;
end

endmodule

module MUX32_5to1(AA0,AA1,AA2,a3,a4,select,out);
	input [31:0]AA0,AA1,AA2,a3,a4;
	input [2:0]select;
	output [31:0]out;
	reg [31:0]out;

always @(AA0 or AA1 or AA2 or a3 or a4 or select) begin
	if(select==0) out=AA0;
	else if(select==1) out=AA1;
	else if(select==2) out=AA2;
	else if(select==3) out=a3;
	else if(select==4) out=a4;
end
endmodule

module MUX32_2to1(AA0, AA1, select, out);
   input [31:0] AA0, AA1;
   input 	select;
   output [31:0] out;
   reg [31:0] 	 out;
   
   always @(AA0 or AA1 or select)
      if (select == 0) out = AA0;
      else          out = AA1;
endmodule // MUX32_2to1


module MUX32_3to1(AA0, AA1, AA2, select, out);
   input [31:0] AA0, AA1, AA2;
   input [1:0] 	select;
   output [31:0] out;
   reg [31:0] 	 out;
   
   always @(AA0 or AA1 or AA2 or select)
      if (select == 0) out = AA0;
      else if (select == 1) out = AA1;
	   else out = AA2;
endmodule // MUX32_3to1


module MUX5_2to1(AA0, AA1, select, out);
   input [4:0]  AA0, AA1;
   input 	select;
   output [4:0] out;
   reg [4:0] 	out;
   
   always @(AA0 or AA1 or select)
      if (select == 0) out = AA0;
      else          out = AA1;
endmodule // MUX5_2to1


module MUX5_3to1(AA0,AA1,AA2,select,out);
	input[4:0] AA0,AA1,AA2;
	input [1:0]select;	
	output[4:0]out;
	reg [4:0] out;

always @(AA0 or AA1 or AA2 or select) begin
	if(select==0) out=AA0;
	else if(select==1) out=AA1;
	else if(select==2) out=AA2;
end

endmodule //MUX5_3to1

module MUX1_2to1(AA0,AA1,select,out);
	input AA0,AA1,select;
	output out;
	reg out;	
always @(AA0 or AA1 or select) begin
	if(select==0)out=AA0;
	else if(select==1)out=AA1;
end

endmodule